US 12,141,679 B2
Mappable filter for neural processor circuit
Waleed Abdulla, Sunnyvale, CA (US); Paolo Di Febbo, Redwood City, CA (US); Mohammad Ghasemzadeh, San Jose, CA (US); and Yohan Rajan, Cupertino, CA (US)
Assigned to APPLE INC., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Oct. 7, 2020, as Appl. No. 17/065,428.
Prior Publication US 2022/0108155 A1, Apr. 7, 2022
Int. Cl. G06N 3/063 (2023.01); G06N 3/04 (2023.01); G06N 3/08 (2023.01)
CPC G06N 3/063 (2013.01) [G06N 3/04 (2013.01); G06N 3/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A neural processor circuit, comprising:
a fetch circuit configured to fetch coefficient data of a machine learning model from a memory source, wherein the coefficient data comprises a plurality of coefficients; and
one or more neural engine circuits coupled to the fetch circuit, at least one of the neural engine circuits comprising:
a buffer circuit configured to receive the coefficient data from the fetch circuit and store the coefficient data;
a coefficient organizing circuit configured to generate at least a first mapping and a second mapping of the coefficient data according to one or more control signals, wherein the first mapping is indicative of a first reading order and the second mapping is indicative of a second reading order, each coefficient of the plurality of coefficients read from the buffer circuit, and wherein the first reading order is different than the second reading order; and
a computation circuit configured to receive and process at least a portion of input data with the coefficient data as mapped according to the first mapping or process at least the portion of the input data with the coefficient data as mapped according to the second mapping.