US 12,141,626 B2
Configurable inter-processor synchronization system
Benoit Dupont de Dinechin, Grenoble (FR); Arnaud Odinot, Grenoble (FR); and Vincent Ray, La Tronche (FR)
Assigned to Kalray, Montbonnot Saint Martin (FR)
Filed by Kalray, Montbonnot Saint Martin (FR)
Filed on Dec. 27, 2019, as Appl. No. 16/729,118.
Claims priority of application No. 18 74270 (FR), filed on Dec. 27, 2018.
Prior Publication US 2020/0210248 A1, Jul. 2, 2020
Int. Cl. G06F 9/30 (2018.01); G06F 9/52 (2006.01); G06F 9/54 (2006.01)
CPC G06F 9/52 (2013.01) [G06F 9/30087 (2013.01); G06F 9/54 (2013.01); G06F 9/522 (2013.01)] 7 Claims
OG exemplary drawing
 
1. An inter-processor synchronization system, comprising:
a plurality of processors;
a plurality of unidirectional notification lines connecting the processors in a chain; and
in each processor:
i) a synchronization register having bits respectively associated with the notification lines, connected to record respective states of upstream notification lines, propagated by an upstream processor, and
ii) a gate controlled by a configuration register to propagate the states of the upstream notification lines on downstream notification lines to a downstream processor;
wherein each processor is configured to;
halt upon execution of a wait machine instruction by the processor, the halt state of the processor being released when the synchronization register of the processor contains a pattern of active bits corresponding to the parameter of the wait instruction, and
selectively activate downstream notification lines according to a parameter of a notification machine instruction executed by the processor.