US 12,141,601 B2
Global coherence operations
Abhijeet Ashok Chachad, Plano, TX (US); Naveen Bhoria, Plano, TX (US); David Matthew Thompson, Dallas, TX (US); and Neelima Muralidharan, Murphy, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Aug. 28, 2023, as Appl. No. 18/456,568.
Application 18/456,568 is a continuation of application No. 17/713,287, filed on Apr. 5, 2022, granted, now 11,740,930.
Application 17/713,287 is a continuation of application No. 16/882,365, filed on May 22, 2020, granted, now 11,294,707, issued on Apr. 5, 2022.
Claims priority of provisional application 62/852,461, filed on May 24, 2019.
Prior Publication US 2023/0409376 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/48 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/448 (2018.01); G06F 9/46 (2006.01); G06F 9/54 (2006.01); G06F 11/30 (2006.01); G06F 12/0804 (2016.01); G06F 12/0811 (2016.01); G06F 12/0813 (2016.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01); G06F 12/0855 (2016.01); G06F 12/0871 (2016.01); G06F 12/0888 (2016.01); G06F 12/0891 (2016.01); G06F 12/12 (2016.01); G06F 12/121 (2016.01); G06F 13/16 (2006.01)
CPC G06F 9/467 (2013.01) [G06F 9/30047 (2013.01); G06F 9/30079 (2013.01); G06F 9/30098 (2013.01); G06F 9/30101 (2013.01); G06F 9/30189 (2013.01); G06F 9/3867 (2013.01); G06F 9/4498 (2018.02); G06F 9/4881 (2013.01); G06F 9/544 (2013.01); G06F 11/3037 (2013.01); G06F 12/0811 (2013.01); G06F 12/0813 (2013.01); G06F 12/0824 (2013.01); G06F 12/0828 (2013.01); G06F 12/0831 (2013.01); G06F 12/0855 (2013.01); G06F 12/0871 (2013.01); G06F 12/0888 (2013.01); G06F 12/0891 (2013.01); G06F 12/12 (2013.01); G06F 13/1668 (2013.01); G06F 12/0804 (2013.01); G06F 12/121 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/621 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A device comprising:
a cache memory;
a processor core configured to provide a global cache operation associated with the cache memory;
a cache controller coupled to the processor core; and
a cache pipeline coupled between the cache controller and the cache memory; wherein the cache controller is configured to, based on the global cache operation:
operate in a first mode where a first type of transaction that includes snoop transactions is not permitted to enter the cache pipeline and a second type of transaction that does not include snoop transactions is permitted to enter the cache pipeline;
based on the cache pipeline being free of the first type of transaction, transition from the first mode to a second mode where the first type of transaction and the second type of transaction are not permitted to enter the cache pipeline; and
based on the cache pipeline being free of transactions, cause the cache pipeline to perform the global cache operation on the cache memory.