US 12,141,584 B2
Power efficient multi-bit storage system
Kai-Chi Huang, Hsinchu (TW); Chi-Lin Liu, New Taipei (TW); Wei-Hsiang Ma, Taipei (TW); and Shang-Chih Hsieh, Yangmei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jul. 7, 2022, as Appl. No. 17/859,377.
Application 17/859,377 is a continuation of application No. 16/900,514, filed on Jun. 12, 2020, granted, now 11,422,819.
Prior Publication US 2022/0334842 A1, Oct. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G11C 11/56 (2006.01)
CPC G06F 9/3844 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30141 (2013.01); G06F 9/3863 (2013.01); G11C 11/5628 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a plurality of storage circuits to update output bits, in response to a trigger signal;
a prediction circuit to generate a trigger enable signal indicating whether at least one of the output bits is predicted to change a state; and
a clock gating circuit, comprising a NAND gate, a plurality of inverters, and a plurality of transistors, to:
generate the trigger signal having a first state, according to a first edge of a clock signal, based on the trigger enable signal, and
maintain the trigger signal having the first state until a second edge of the clock signal subsequent to the first edge.