CPC G06F 9/384 (2013.01) [G06F 9/3012 (2013.01); G06F 9/3891 (2013.01)] | 20 Claims |
19. A method comprising:
performing, by processing circuitry comprising execution units, operations;
storing, by a plurality of physical registers, data accessed by the execution units to perform the operations;
forwarding the data from the physical registers to the execution units over an incomplete set of connections between the physical registers and the execution units such that, for each of at least some of the physical registers, the physical register is connected to a proper subset of the execution units;
mapping logical registers identified by the operations to respective physical registers of the plurality of physical registers; and
monitoring upcoming operations to be performed by the processing circuitry and determining, based on the upcoming operations and the incomplete set of connections, whether to perform a register reorganisation procedure to change a mapping between the logical registers and the physical registers;
performing, in response to determining to perform the register reorganisation procedure, the register reorganisation procedure.
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