US 12,141,581 B2
Predictive dead store elimination
Shimin Cui, North York (CA); Wai Hung Tsang, Markham (CA); Hubert Shun Kwan Tong, Scarborough (CA); and Zarko Todorovski, Ajax (CA)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jan. 23, 2023, as Appl. No. 18/157,990.
Prior Publication US 2024/0248716 A1, Jul. 25, 2024
Int. Cl. G06F 9/30 (2018.01); G06F 8/41 (2018.01); G06F 9/32 (2018.01)
CPC G06F 9/30043 (2013.01) [G06F 8/4435 (2013.01); G06F 9/325 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method for predictive dead store elimination by a compiler optimization technique performed by a compiler executing on a data processing system comprising a number of processors, the method comprising:
using the number of processors to perform the steps of:
identifying, in a program by the compiler, a first store operation and a second store operation in a program loop that comprise a store pair with a same loop-invariant base address;
determining, by the compiler, whether the store pair is a predictive dead store elimination candidate;
responsive to a determination that the store pair is a predictive dead store elimination candidate:
eliminating, by the compiler, the first store operation in each iteration of the program loop, except last dead store recurrence constant (DSRC) iterations; and
sinking, by the compiler, the first store operation in the last DSRC iterations to after the program loop, wherein a size of the program is reduced by the compiler optimization technique.