US 12,141,512 B1
Method, product, and system for universal verification methodology (UVM) sequence selection using machine learning
Shadi Saba, San Jose, CA (US); Roque Alejandro Arcudia Hernandez, San Jose, CA (US); Uyen Huynh Ha Nguyen, San Jose, CA (US); Pedro Eugênio Rocha Medeiros, Serra-Belo Horizone/MG (BR); and Claire Liyan Ying, Los Altos Hills, CA (US)
Assigned to Cadence Design Systems, Inc., San Jose, CA (US)
Filed by Cadence Design Systems, Inc., San Jose, CA (US)
Filed on Sep. 30, 2021, as Appl. No. 17/490,462.
Int. Cl. G06F 30/33 (2020.01); G06F 30/333 (2020.01); G06N 7/01 (2023.01); G06N 20/00 (2019.01)
CPC G06F 30/33 (2020.01) [G06F 30/333 (2020.01); G06N 7/01 (2023.01); G06N 20/00 (2019.01)] 20 Claims
OG exemplary drawing
 
1. A method for universal verification methodology (UVM) sequence selection comprising:
identifying a state representation of a current state of at least a design under test;
selecting an action or sequence of actions to be executed at the design under test by at least processing the state representation using a machine learning model, wherein a vector representing at least a subset of the current state is input into the machine learning model, the machine learning model outputs a probability distribution in response to the vector, and the probability distribution is mapped to multiple actions or sequences of actions; and
executing the selected action or sequence of actions at the design under test.