US 12,141,511 B2
Automated circuit generation
Calum MacRae, Charlotte, NC (US); John Mason, Sunnyvale, CA (US); and Karen Mason, Sunnyvale, CA (US)
Assigned to Celera, Inc., San Jose, CA (US)
Filed by Celera, Inc., San Jose, CA (US)
Filed on May 8, 2023, as Appl. No. 18/314,012.
Application 18/314,012 is a continuation of application No. 17/507,504, filed on Oct. 21, 2021, granted, now 11,694,007.
Application 17/507,504 is a continuation of application No. 16/886,544, filed on May 28, 2020, granted, now 11,361,134, issued on Jun. 14, 2022.
Application 16/886,544 is a continuation of application No. 16/882,217, filed on May 22, 2020.
Claims priority of provisional application 62/854,848, filed on May 30, 2019.
Prior Publication US 2023/0274058 A1, Aug. 31, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/327 (2020.01); G06F 30/31 (2020.01); G06F 30/347 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/38 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 111/12 (2020.01)
CPC G06F 30/327 (2020.01) [G06F 30/31 (2020.01); G06F 30/347 (2020.01); G06F 30/367 (2020.01); G06F 30/38 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/373 (2020.01); G06F 2111/12 (2020.01)] 30 Claims
OG exemplary drawing
 
1. A computer-implemented method of generating a capacitor comprising:
receiving a total capacitance for a capacitor to be generated;
determining a number N of unit capacitors having a unit capacitance to be combined to form the total capacitance;
generating a transistor level schematic comprising N unit capacitor schematics having the unit capacitance, wherein the N unit capacitor schematics are configured to produce the total capacitance; and
generating a layout comprising N capacitor layout elements configured to produce said capacitor.