US 12,141,478 B2
Memory device, memory module including the memory device, and operating method of memory controller
Deokho Seo, Suwon-si (KR); Taekyeong Ko, Hwaseong-si (KR); Namhyung Kim, Seoul (KR); Daejeong Kim, Seoul (KR); Dohan Kim, Hwaseong-si (KR); Hoyoung Lee, Osan-si (KR); and Insu Choi, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 16, 2022, as Appl. No. 17/932,734.
Claims priority of application No. 10-2021-0147163 (KR), filed on Oct. 29, 2021.
Prior Publication US 2023/0137339 A1, May 4, 2023
Int. Cl. G06F 3/06 (2006.01); H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0673 (2013.01); H03M 13/1111 (2013.01); H03M 13/611 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory cell array comprising a normal region in which first data is stored and a parity region in which a parity bit for the first data is stored;
an error correction code (ECC) engine configured to determine whether there is an error in the first data, based on the first data and the parity bit,
wherein the ECC engine is further configured to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected;
a plurality of pins connected to the memory controller; and
a command decoder configured to separately receive a normal read command and the uncorrected read command based on at least one of the plurality of pins,
wherein the normal read command is configured to correct the error bit in the first data,
wherein the ECC engine is further configured to generate corrected data by correcting the error bit and output the second data instead of the corrected data, in response to receiving a control signal based on the uncorrected read command from the command decoder.