US 12,141,470 B2
Feedback for multi-level signaling in a memory device
M. Ataul Karim, Boise, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Jan. 3, 2024, as Appl. No. 18/403,512.
Application 18/403,512 is a continuation of application No. 18/056,520, filed on Nov. 17, 2022, granted, now 11,880,591.
Application 18/056,520 is a continuation of application No. 17/208,885, filed on Mar. 22, 2021, granted, now 11,543,995, issued on Jan. 3, 2023.
Prior Publication US 2024/0256173 A1, Aug. 1, 2024
Int. Cl. G06F 3/06 (2006.01); G11C 11/22 (2006.01); G11C 11/4076 (2006.01); H03F 3/45 (2006.01); H03K 3/356 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 11/2293 (2013.01); G11C 11/4076 (2013.01); H03F 3/45179 (2013.01); H03K 3/356113 (2013.01); G11C 11/221 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A dynamic random-access memory (DRAM) device, comprising:
a receiver of a decision feedback equalization (DFE) circuit coupled with a Data In or Out (DQ) channel and configured to receive a signal, the receiver comprising a multi-phase architecture, and the receiver comprising:
a first slicer circuit configured to determine a voltage level at a first clock phase of the signal;
a first feedback circuit coupled with an input of a second slicer circuit and an output of the first slicer circuit, the first feedback circuit configured to receive a first feedback signal from the first slicer circuit and modify the signal input into the second slicer circuit based at least in part on a first parameter associated with a first mode register of the DRAM device;
the second slicer circuit configured to determine a voltage level at a second clock phase of the signal;
a second feedback circuit coupled with an input of a third slicer circuit and an output of the second slicer circuit, the second feedback circuit configured to receive a second feedback signal from the second slicer circuit and modify the signal input into the third slicer circuit based at least in part on a second parameter associated with a second mode register of the DRAM device; and
the third slicer circuit configured to determine a voltage level at a third clock phase of the signal.