US 12,141,468 B1
Matrix transpose hardware acceleration
Kun Xu, Austin, TX (US); Paul Gilbert Meyer, Rollingwood, TX (US); and Ron Diamant, Santa Clara, CA (US)
Assigned to Amazon Technologies, Inc., Seattle, WA (US)
Filed by Amazon Technologies, Inc., Seattle, WA (US)
Filed on Jul. 28, 2022, as Appl. No. 17/875,805.
Application 17/875,805 is a continuation of application No. 16/911,127, filed on Jun. 24, 2020, granted, now 11,435,941.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06N 3/02 (2006.01); G06N 5/04 (2023.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06N 3/02 (2013.01); G06N 5/04 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first memory;
a second memory; and
a memory access circuit configured to:
concurrently during a set of clock cycles:
perform read operations in a first orientation to read a first data matrix from the first memory; and
perform write operations in the first orientation to write a second data matrix to the first memory; and
perform write operations in a second orientation to write the first data matrix to the second memory;
wherein the second orientation is different from the first orientation, and wherein either (i) the first orientation is a column-wise orientation and the second orientation is a row-wise orientation or (ii) the first orientation is a row-wise orientation and the second orientation is a column-wise orientation.