	US 12,141,450 B2
	Processors, methods and systems to allow secure communications between protected container memory and input/output devices
Ilya Alexandrovich, Haifa (IL); Vladimir Beker, Ariel (IL); Gideon Gerzon, Zichron Yaakov (IL); and Vincent R. Scarlata, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Dec. 16, 2022, as Appl. No. 18/083,277.
Application 18/083,277 is a continuation of application No. 16/882,637, filed on May 25, 2020, granted, now 11,531,475.
Application 16/882,637 is a continuation of application No. 14/866,478, filed on Sep. 25, 2015, granted, now 10,664,179, issued on May 26, 2020.
Prior Publication US 2023/0266888 A1, Aug. 24, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 21/78 (2013.01); G06F 21/79 (2013.01); G06F 21/85 (2013.01)

CPC G06F 3/0622 (2013.01) [G06F 3/0637 (2013.01); G06F 3/0673 (2013.01); G06F 13/16 (2013.01); G06F 13/4068 (2013.01); G06F 21/78 (2013.01); G06F 21/79 (2013.01); G06F 21/85 (2013.01)]

25 Claims

1. A processor comprising:

first circuitry to receive binary code and configuration information associated with the binary code, the configuration information including an address of a page of a protected container, an identifier corresponding to a memory-mapped input/output (MMIO) device, and an MMIO space offset; and

second circuitry to perform operations corresponding to the binary code, including to:

perform a plurality of security checks, including to:

check that the identifier is mapped to the protected container; and

check that a type of the page is an input/output type; and

if the plurality of security checks succeed, configure the page to allow for secure MMIO with the MMIO device.