| CPC G06F 3/0619 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |

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1. A memory device comprising:
a memory block comprising a first adjacent word line, a selected word line, and a second adjacent word line provided in a direction perpendicular to a substrate; and
an address decoding circuit,
wherein, in a first setup period in which the selected word line is set up for a programming operation, the first setup period comprising a start time point and an end time point, the address decoding circuit is configured to:
apply a first pre-setup voltage to the first adjacent word line between the start time point of the first setup period and a first time point;
apply a first setup voltage that is higher than the first pre-setup voltage to the first adjacent word line between the first time point and the end time point of the first setup period;
apply a second pre-setup voltage to the second adjacent word line between the start time point of the first setup period and a second time point; and
apply a second setup voltage that is higher than the second pre-setup voltage to the second adjacent word line between the second time point and the end time point of the first setup period, and
wherein the first pre-setup voltage is higher than the second pre-setup voltage.
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