US 12,141,438 B2
Zero skipping techniques for reducing data movement
Fei Xue, Sunnyvale, CA (US); Fei Sun, San Jose, CA (US); Yangjie Zhou, Shanghai (CN); Lide Duan, Sunnyvale, CA (US); and Hongzhong Zheng, Los Gatos, CA (US)
Assigned to Alibaba Group Holding Limited, Grand Cayman (KY)
Appl. No. 17/779,523
Filed by Alibab Group Holding Limited, Grand Cayman (KY)
PCT Filed Feb. 25, 2021, PCT No. PCT/CN2021/077990
§ 371(c)(1), (2) Date May 24, 2022,
PCT Pub. No. WO2022/178791, PCT Pub. Date Sep. 1, 2022.
Prior Publication US 2023/0161479 A1, May 25, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
a processor sparsity control unit configured to generate a zero skipping sparsity command, wherein the zero skipping sparsity command includes a memory access request; and
a command interface configured to:
transmit the zero skipping sparsity command to a memory based on the memory access request, wherein the zero skipping sparsity command comprises a zero skipping command identifier (TAGID) and a computation operation code (OP); and
receive from the memory, given elements from a first set of elements and a second set of elements and the zeroskipping command identifier (TAGID), in response to the zero skipping sparsity command, wherein the zeroskipping command identifier (TAGID) identifies the zero skipping sparsity command;
wherein the processor is further configured to:
perform a computation operation based on the computation operation code (OP) of the zero skipping sparsity command, on the received given elements of the first set of elements and the second set of elements to generate result elements, and
wherein the command interface is further configured to transmit the result elements and the zeroskipping command identifier (TAGID) to the memory.