US 12,141,330 B2
Multiple key management
Daniel John Pelham Wilkinson, Bristol (GB); Graham Bernard Cunningham, Chippenham (GB); Stavros Volos, Cambridge (GB); Kapil Vaswani, Cambridge (GB); Cedric Alain Marie Fournet, Cambridge (GB); and Balaji Vembu, Folsom, CA (US)
Assigned to GRAPHCORE LTD., Bristol (GB)
Filed by Graphcore Limited, Bristol (GB)
Filed on Jul. 13, 2021, as Appl. No. 17/374,925.
Claims priority of application No. 2010823 (GB), filed on Jul. 14, 2020.
Prior Publication US 2022/0019700 A1, Jan. 20, 2022
Int. Cl. G06F 21/72 (2013.01); G06F 3/06 (2006.01); G06F 21/78 (2013.01); H04L 9/06 (2006.01); H04L 9/08 (2006.01); H04L 9/14 (2006.01); H04L 9/32 (2006.01)
CPC G06F 21/72 (2013.01) [G06F 3/0623 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01); G06F 21/78 (2013.01); H04L 9/0618 (2013.01); H04L 9/0631 (2013.01); H04L 9/0894 (2013.01); H04L 9/14 (2013.01); H04L 9/3242 (2013.01)] 29 Claims
OG exemplary drawing
 
1. An integrated circuit for acting as an accelerator subsystem for processing data received from a storage, the integrated circuit comprising:
a processing unit comprising a plurality of sets of processors, wherein each of the processors is operable to issue read requests to read data from the storage;
at least one encryption unit comprising a memory configured to store a plurality of keys, wherein each of at least some of the keys are associated with different ones of the sets of processors, wherein the at least one encryption unit comprises processing circuitry configured to:
receive a read completion formed in response to a read request issued by a first processor belonging to one of the sets of processors, the read completion comprising data read from the storage;
identify from one or more identifier bits in the read completion, a first key of the plurality of keys that is associated with the one of the sets of processors to which the first processor belongs;
using the first key, perform decryption operations with respect to the data contained in the read completion to form decrypted data; and
cause the read completion to be returned to the first processor with the decrypted data,
wherein the at least one encryption unit comprises a plurality of context storages, each of the context storages being for storing state information associated with an encryption frame comprising a plurality of read completions, wherein each of the context storages is associated with one or more of the sets of processors,
wherein the processing circuitry of the at least one encryption unit is configured to:
identify from the one or more identifier bits, one of the context storages associated with the one of the sets of processors comprising the first processor; and
use the identified one of the context storages for storing state information associated with an encryption frame comprising the read completion.