US 12,141,226 B2
Systems and processes for organizing and controlling multiple matrix processor circuits
Siyad Chih-Hua Ma, Palo Alto, CA (US); Shang-Tse Chuang, Los Altos, CA (US); and Sharad Vasantrao Chole, San Jose, CA (US)
Assigned to Expedera, Inc., Santa Clara, CA (US)
Filed by Expedera, Inc., Santa Clara, CA (US)
Filed on Apr. 5, 2019, as Appl. No. 16/377,103.
Claims priority of provisional application 62/791,585, filed on Jan. 11, 2019.
Prior Publication US 2020/0226201 A1, Jul. 16, 2020
Int. Cl. G06F 17/16 (2006.01); G06N 3/04 (2023.01)
CPC G06F 17/16 (2013.01) [G06N 3/04 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A digital processing circuit, said digital processing circuit comprising:
a plurality of matrix processing units, said plurality of matrix processing units arranged into a matrix processor array comprising a plurality of rows and columns of the matrix processing units, each of said matrix processing units comprising:
a left operand bus for receiving a first operand vector, the first operand vector comprising a plurality of operands, the left operand bus being a plurality of operands wide;
a right result bus for outputting a result vector, the result vector comprising a plurality of result values, said right result bus being the plurality of result values wide;
a memory for storing matrix data;
a processing system for performing matrix operation, and a command input for receiving control commands;
a plurality of combiner circuits, each said combiner circuits coupled to said right result bus such that result vectors from matrix processing units in a common row are combined with a first function; and
a control system, said control system for loading weight matrices into said plurality of matrix processing units, loading in said first operand vector, and requesting a matrix operation by sending a control command on said command input.