US 12,141,092 B2
Instruction set
Simon Christian Knowles, Corston (GB); Daniel John Pelham Wilkinson, West Harptree (GB); Richard Luke Southwell Osborne, Bristol (GB); Alan Graham Alexander, Wotton-Under-Edge (GB); Stephen Felix, Bristol (GB); Jonathan Mangnall, Portishead (GB); and David Lacey, Cheltenham (GB)
Assigned to GRAPHCORE LIMTIED, Bristol (GB)
Filed by Graphcore Limited, Bristol (GB)
Filed on Apr. 6, 2022, as Appl. No. 17/658,124.
Application 17/658,124 is a continuation of application No. 15/886,131, filed on Feb. 1, 2018, granted, now 11,321,272.
Claims priority of application No. 1717299 (GB), filed on Oct. 20, 2017.
Prior Publication US 2022/0253399 A1, Aug. 11, 2022
Int. Cl. G06F 15/173 (2006.01); G06F 8/41 (2018.01); G06F 9/38 (2018.01); G06F 15/80 (2006.01)
CPC G06F 15/17312 (2013.01) [G06F 8/456 (2013.01); G06F 9/3885 (2013.01); G06F 15/17325 (2013.01); G06F 15/17337 (2013.01); G06F 15/80 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A device comprising:
a first processing unit, having a first memory for storing a first local program and a first execution unit for executing instructions of the first local program, wherein the first processing unit is configured to operate in a first compute phase, during which the first execution unit performs computations, and an exchange phase, during which the first processing unit exchanges data;
a second processing unit, having a second memory for storing a second local program and a second execution unit for executing instructions of the second local program, wherein the second processing unit is configured to operate in a second compute phase, during which the second execution unit performs computations, and the exchange phase, during which the second processing unit exchanges data;
a switching fabric comprising a plurality of connecting wires configured to exchange the data between the first processing unit and the second processing unit; and
synchronisation controller circuitry configured to issue a synchronisation signal to the first processing unit and the second processing unit, wherein a thread running on the first execution unit is configured to proceed to the exchange phase in response to receipt of the synchronisation signal at the first processing unit,
wherein the first execution unit is configured to, during the exchange phase, execute a send instruction from the first local program to transmit, during a first clock cycle that is defined at compile time, a data packet over the switching fabric,
wherein the switching fabric is configured to transport the data packet to the second processing unit in a predefined number of clock cycles, such that the data packet is received at the second processing unit at a receive time that is defined at compile time.