US 12,141,091 B2
Semiconductor device and memory system
Kunihiko Yamagishi, Yokohama (JP); and Toshitada Saito, Yokohama (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Aug. 3, 2023, as Appl. No. 18/364,970.
Application 18/364,970 is a continuation of application No. 17/500,581, filed on Oct. 13, 2021, granted, now 11,762,800.
Application 17/500,581 is a continuation of application No. 17/100,161, filed on Nov. 20, 2020, granted, now 11,176,079, issued on Nov. 16, 2021.
Application 17/100,161 is a continuation of application No. 16/593,508, filed on Oct. 4, 2019, granted, now 10,877,917, issued on Dec. 29, 2020.
Application 16/593,508 is a continuation of application No. 15/978,272, filed on May 14, 2018, granted, now 10,482,052, issued on Nov. 19, 2020.
Application 15/978,272 is a continuation of application No. 15/627,821, filed on Jun. 20, 2017, granted, now 9,996,493, issued on Jun. 12, 2018.
Application 15/627,821 is a continuation of application No. 15/257,666, filed on Sep. 6, 2016, granted, now 9,720,870, issued on Aug. 1, 2017.
Application 15/257,666 is a continuation of application No. 14/797,970, filed on Jul. 13, 2015, granted, now 9,471,527, issued on Oct. 18, 2016.
Application 14/797,970 is a continuation of application No. 14/292,180, filed on May 30, 2014, granted, now 9,111,048, issued on Aug. 18, 2015.
Application 14/292,180 is a continuation of application No. 13/514,736, granted, now 8,781,024, issued on Jul. 15, 2014, previously published as PCT/JP2010/066464, filed on Sep. 15, 2010.
Claims priority of application No. 2009-279719 (JP), filed on Dec. 9, 2009.
Prior Publication US 2023/0376440 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/42 (2006.01); G06F 12/02 (2006.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01); H04L 25/03 (2006.01)
CPC G06F 13/4068 (2013.01) [G06F 12/0246 (2013.01); G06F 13/385 (2013.01); G06F 13/40 (2013.01); G06F 13/4063 (2013.01); G06F 13/42 (2013.01); G06F 13/4282 (2013.01); H04L 25/03828 (2013.01); G06F 2212/7201 (2013.01); G06F 2213/3804 (2013.01); G06F 2213/3854 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A device capable of communicating with a host apparatus, comprising:
a symbol generation unit which includes a random number generation circuit, the symbol generation unit configured to select one of a first symbol and a second symbol in a random order with use of the random number generation circuit and output the selected one of the symbols;
a coding unit which performs coding a signal of the outputted symbol to transform a bit number; and
a transmission unit which transmits the symbol coded by the coding unit to the host apparatus,
wherein the first symbol and the second symbol indicate an idle state,
wherein the coded symbol is transmitted to the host apparatus by the transmission unit,
wherein each of the first and second symbols includes a pair of symbols including a symbol as a plus running disparity and another symbol as a minus running disparity,
wherein if a symbol which was most recently selected by the random number generation circuit had a plus running disparity, a symbol selected by the random number generation circuit becomes a minus running disparity, and
wherein if a symbol which was most recently selected by the random number generation circuit had a minus running disparity, a symbol selected by the random number generation circuit becomes a plus running disparity.