	US 12,141,084 B2
	Separate inter-die connectors for data and error correction information and related computing systems, methods, and apparatuses
Vijayakrishna J. Vankayala, Allen, TX (US)
Assigned to Lodestar Licensing Group LLC, Evanston, IL (US)
Filed by Lodestar Licensing Group, LLC, Evanston, IL (US)
Filed on Aug. 4, 2023, as Appl. No. 18/365,794.
Application 18/365,794 is a continuation of application No. 17/807,186, filed on Jun. 16, 2022, granted, now 11,755,506.
Application 17/807,186 is a continuation of application No. 16/819,914, filed on Mar. 16, 2020, granted, now 11,366,772, issued on Jun. 21, 2022.
Prior Publication US 2023/0376432 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01); G06F 13/16 (2006.01); H01L 25/065 (2023.01)

CPC G06F 13/1668 (2013.01) [G06F 11/1004 (2013.01); G06F 11/1076 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06586 (2013.01)]

20 Claims

18. An apparatus, comprising:

a master die configured to:

receive read data bits from a target die via inter-die data connectors;

receive error correction information corresponding to the read data bits from the target die via inter-die error connection connectors separate from the inter-die data connectors; and

provide the read data bits and the error correction information to control circuitry;

the control circuitry configured to:

request a read operation;

receive, from the master die, the read data bits and the error correction information corresponding to the read data bits responsive to the request for the read operation;

obtain new error correction information corresponding to the read data bits using error correction circuitry; and

repeat the request for the read operation responsive to a determination that the error correction information is different from the new error correction information.