| CPC G06F 13/1663 (2013.01) | 25 Claims |
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1. A parallel processor comprising:
a memory interface;
a plurality of processors; and
a plurality of memory access hardware circuits, each memory access hardware circuit being coupled to a processor of the plurality of processor and being configured to:
receive, from the coupled processor, a memory access request for a multidimensional data structure, the memory access request specifying a coordinate of the multidimensional data structure; and
in response to the memory access request, translate at least the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure between a location in an external memory accessed through the memory interface and a location in a shared memory of the coupled processor,
wherein said at least the coordinate defines a location of a block of data within the multidimensional data structure stored in the external memory,
wherein the memory access hardware circuit coupled to the processor is further configured to determine whether the block of data is a portion in a tensor stored in the external memory or whether the block of data comprises non-tensor data in the external memory.
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