US 12,141,078 B2
Victim cache with dynamic allocation of entries
Naveen Bhoria, Plano, TX (US); Timothy David Anderson, University Park, TX (US); and Pete Hippleheuser, Murphy, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on May 22, 2020, as Appl. No. 16/882,395.
Claims priority of provisional application 62/852,494, filed on May 24, 2019.
Prior Publication US 2020/0371963 A1, Nov. 26, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/128 (2016.01); G06F 9/30 (2018.01); G06F 9/54 (2006.01); G06F 11/10 (2006.01); G06F 12/02 (2006.01); G06F 12/0802 (2016.01); G06F 12/0804 (2016.01); G06F 12/0806 (2016.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0817 (2016.01); G06F 12/0853 (2016.01); G06F 12/0855 (2016.01); G06F 12/0864 (2016.01); G06F 12/0884 (2016.01); G06F 12/0888 (2016.01); G06F 12/0891 (2016.01); G06F 12/0895 (2016.01); G06F 12/0897 (2016.01); G06F 12/12 (2016.01); G06F 12/121 (2016.01); G06F 12/126 (2016.01); G06F 12/127 (2016.01); G06F 13/16 (2006.01); G06F 15/80 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01)
CPC G06F 12/128 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/546 (2013.01); G06F 11/1064 (2013.01); G06F 12/0215 (2013.01); G06F 12/0238 (2013.01); G06F 12/0292 (2013.01); G06F 12/0802 (2013.01); G06F 12/0804 (2013.01); G06F 12/0806 (2013.01); G06F 12/0811 (2013.01); G06F 12/0815 (2013.01); G06F 12/082 (2013.01); G06F 12/0853 (2013.01); G06F 12/0855 (2013.01); G06F 12/0864 (2013.01); G06F 12/0884 (2013.01); G06F 12/0888 (2013.01); G06F 12/0891 (2013.01); G06F 12/0895 (2013.01); G06F 12/0897 (2013.01); G06F 12/12 (2013.01); G06F 12/121 (2013.01); G06F 12/126 (2013.01); G06F 12/127 (2013.01); G06F 13/1605 (2013.01); G06F 13/1642 (2013.01); G06F 13/1673 (2013.01); G06F 13/1689 (2013.01); G06F 15/8069 (2013.01); G11C 5/066 (2013.01); G11C 7/10 (2013.01); G11C 7/1015 (2013.01); G11C 7/106 (2013.01); G11C 7/1075 (2013.01); G11C 7/1078 (2013.01); G11C 7/1087 (2013.01); G11C 7/222 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1041 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/301 (2013.01); G06F 2212/454 (2013.01); G06F 2212/603 (2013.01); G06F 2212/6032 (2013.04); G06F 2212/6042 (2013.01); G06F 2212/608 (2013.01); G06F 2212/62 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A caching system comprising:
a first sub-cache; and
a second sub-cache coupled in parallel with the first sub-cache, wherein:
the second sub-cache includes a set of lines and a set of line type bits;
each line of the set of lines is configured to operate in a first manner to store a respective set of data associated with a write-miss and operate in a second manner to store a respective set of data associated with an eviction of a cache entry from the first sub-cache; and
each line type bit of the set of line type bits is configured to store a first indication based on that a respective set of data of a respective line of the set of lines is associated with a write-miss and a second indication based on that the respective set of data is associated with an eviction of a cache entry from the first sub-cache.