CPC G06F 12/0891 (2013.01) [G06F 12/1027 (2013.01)] | 20 Claims |
1. An integrated circuit comprising:
a cache memory; and
a store queue coupled to the cache memory and configured to:
store a first address and a first set of data associated with an instruction;
receive a second address associated with an eviction of a second set of data from the cache memory;
determine whether the first address and the second address are the same; and
based on the first address and the second address being the same, invalidate the first set of data in the store queue.
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