| CPC G06F 12/0875 (2013.01) [G06F 2212/60 (2013.01)] | 20 Claims |
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1. A processor included within a central processing unit (CPU), the CPU included within a computer processor system, the CPU coupled to a memory, the processor comprising:
a load and store unit (LSU) including an LSU control module and an LSU store queue, the LSU store queue including a first plurality of entries for storing a first plurality of information packets;
a cache memory (L2 cache) coupled to the LSU, the L2 cache including an L2 cache control module and an L2 cache store queue, the L2 cache store queue including a second plurality of entries for storing a second plurality of information packets;
wherein the L2 cache determines that a free entry of the second plurality of entries exists in the L2 cache store queue, and transmits a request to the LSU to transfer an information packet of the first plurality of information packets based on the determination that the free entry exists in the L2 cache;
wherein the LSU transmits, based on the request, an acknowledgement to the L2 cache and transfers the information packet from an entry of the first plurality of entries in the LSU store queue over a data bus coupled to the L2 cache;
wherein the acknowledgement is different from the information packet;
wherein the L2 cache receives the information packet from the LSU store queue and stores the information packet in the free entry in the L2 cache store queue; and
wherein, before the L2 cache requests an additional information packet from the first plurality of information packets, the LSU anticipates that the L2 cache store queue has an additional free entry in the second plurality of entries, transmits an additional acknowledgement to the L2 cache, and transfers the additional information packet from an additional entry in the first plurality of entries in the LSU store queue.
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