US 12,141,038 B2
Error recovery for non-volatile memory modules
Jing Wang, Austin, TX (US); James R. Magro, Austin, TX (US); and Kedarnath Balakrishnan, Bangalore (IN)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 19, 2022, as Appl. No. 18/084,350.
Application 18/084,350 is a continuation of application No. 16/729,994, filed on Dec. 30, 2019, granted, now 11,531,601.
Prior Publication US 2023/0125792 A1, Apr. 27, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/14 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/1474 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/068 (2013.01); G06F 2201/82 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller embodied in an integrated circuit, comprising:
an arbiter for selecting memory access commands, including volatile reads, volatile writes, non-volatile reads, and non-volatile writes, for transmission over a heterogeneous memory channel to at least one storage class memory (SCM) module;
at least one storage queue storing memory access commands that are selected for transmission; and
a replay control circuit for, responsive to an error condition, initiating a recovery sequence in which the replay control circuit transmits the selected memory access commands from the at least one storage queue by grouping non-volatile read commands together separately from all pending volatile reads, volatile writes, and non-volatile writes.