US 12,141,030 B2
Accessing error statistics from DRAM memories having integrated error correction
Siva Srinivas Kothamasu, Frisco, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jul. 31, 2023, as Appl. No. 18/361,995.
Application 18/361,995 is a continuation of application No. 17/878,149, filed on Aug. 1, 2022, granted, now 11,714,713.
Application 17/878,149 is a continuation of application No. 16/789,672, filed on Feb. 13, 2020, granted, now 11,403,171, issued on Aug. 2, 2022.
Application 16/789,672 is a continuation of application No. 15/961,010, filed on Apr. 24, 2018, granted, now 10,572,344, issued on Feb. 25, 2020.
Claims priority of provisional application 62/490,709, filed on Apr. 27, 2017.
Prior Publication US 2023/0376377 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 13/16 (2006.01); G11C 5/04 (2006.01); G11C 29/04 (2006.01); G11C 29/52 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/1048 (2013.01); G06F 13/1668 (2013.01); G11C 29/52 (2013.01); G06F 2213/0016 (2013.01); G11C 5/04 (2013.01); G11C 2029/0411 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A system comprising:
a memory circuit that includes:
a memory array;
a configuration register;
a first interface coupled to the configuration register;
a statistics register; and
a second interface coupled to the statistics register, wherein the second interface is distinct from the first interface; and
a processing circuit that includes:
a third interface configured to couple to the first interface of the memory circuit and configured to provide a first transaction that accesses the configuration register via the first interface; and
a fourth interface configured to couple to the second interface of the memory circuit and configured to provide a second transaction that accesses the statistics register via the second interface.