US 12,141,029 B2
Internal error correction for memory devices
Aaron P. Boehm, Boise, ID (US); and Scott E. Schaefer, Boise, ID (US)
Filed by Lodestar Licensing Group, LLC, Evanston, IL (US)
Filed on Aug. 2, 2023, as Appl. No. 18/229,547.
Application 18/229,547 is a continuation of application No. 17/869,775, filed on Jul. 20, 2022, granted, now 11,755,409.
Application 17/869,775 is a continuation of application No. 17/152,036, filed on Jan. 19, 2021, granted, now 11,436,082, issued on Sep. 6, 2022.
Claims priority of provisional application 62/975,138, filed on Feb. 11, 2020.
Prior Publication US 2024/0028454 A1, Jan. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 11/30 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/0772 (2013.01); G06F 11/1048 (2013.01); G06F 11/3037 (2013.01)] 20 Claims
OG exemplary drawing
 
20. A method by a memory device, comprising:
receiving a write command at the memory device partitioned into a first partition and a second partition, the write command comprising a set of data bits;
storing the set of data bits and one or more parity bits to a first partition, and a set of error control bits associated with the set of data bits to the second partition based at least in part on receiving the write command;
receiving a read command;
performing a first error control operation using the set of data bits and the set of error control bits based at least in part on receiving the read command;
performing a second error control operation using the one or more parity bits based at least in part on receiving the read command; and
transmit an indication of one or more errors in the set of data bits based at least in part on performing the first error control operation and the second error control operation.