| CPC G06F 1/3287 (2013.01) [G06F 1/3228 (2013.01)] | 17 Claims |
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1. An apparatus comprising:
a plurality of processing cores; and
a power management controller associated with the plurality of processing cores,
wherein the power management controller is to receive one or more hints from an operating system indicative of a bias towards energy efficiency or performance for the plurality of processing cores, or subsets thereof, based on characteristics of corresponding threads to be scheduled for execution on the plurality of processing cores or subsets thereof,
the power management controller, based on the characteristics, to differentiate between latency-sensitive or performance-sensitive threads and less latency-sensitive or performance-sensitive threads and to responsively cause a first processing core associated with a latency-sensitive or performance-sensitive thread to utilize a relatively shallower idle state and to cause a second processing core associated with a less latency-sensitive or performance-sensitive thread to utilize a relatively deeper idle state;
wherein the operating system is to determine during a context switch the latency-sensitive or performance-sensitive thread is a high priority thread and is to update a register or a table to include the first processing core based on the latency-sensitive or performance-sensitive thread being a high priority thread, wherein the register or table relates to an affinity to shallow idle state setting.
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