| CPC G05F 1/59 (2013.01) [G05F 3/262 (2013.01)] | 17 Claims |
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1. An apparatus comprising:
a first transistor having a first drain/source terminal coupled to an input terminal of a regulator, and a second drain/source terminal coupled to an output terminal of the regulator;
a second transistor having a first drain/source terminal coupled to the input terminal of the regulator, and a second drain/source terminal coupled to the output terminal of the regulator through a resistor, and wherein the second drain/source terminal of the second transistor is connected to ground through a voltage divider;
an error amplifier having an inverting input configured to receive a reference, a non-inverting input connected to the second drain/source terminal of the second transistor through the voltage divider, and an output coupled to gates of the first transistor and the second transistor, and wherein the resistor and the voltage divider are connected in series between the output terminal of the regulator and ground, and a midpoint of the voltage divider is connected to the non-inverting input of the error amplifier; and
an output capacitor coupled between the output terminal of the regulator and ground, wherein the resistor and the output capacitor form a zero to compensate a pole of the regulator, and wherein the pole of the regulator is formed by an output resistance of a stage coupled to the gate of the first transistor and an input capacitance of the first transistor, and wherein a ratio of a size of the first transistor to a size of the second transistor is equal to (N:1), and wherein as a result of having the first transistor N times greater than the second transistor, a frequency of the zero is inversely proportional to a capacitance value of the output capacitor times a resistance value of the resistor divided by (N+1).
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