US 12,140,982 B2
Time based predictive maintenance for capacitive loads in factory automation applications
Domenico Ragonese, Tremestrieri Etneo (IT); Vincenzo Marano, Cinisello Balsamo (IT); Giuseppe Antonio Di Genova, Pozzallo (IT); and Marco Minieri, Catania (IT)
Assigned to STMicroelctronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Jul. 18, 2022, as Appl. No. 17/866,701.
Prior Publication US 2024/0019885 A1, Jan. 18, 2024
Int. Cl. G05F 1/573 (2006.01)
CPC G05F 1/573 (2013.01) 19 Claims
OG exemplary drawing
 
1. A system, comprising:
a power transistor having a first conduction terminal coupled to a supply node, a second conduction terminal coupled to a load node, and a control terminal controlled by a drive signal;
a driver configured to receive an input voltage from an external component and generate the drive signal based thereupon;
a sense circuit configured to, when the power transistor is powering a load coupled to the load node:
detect whether the power transistor has entered an overload condition, and if so, determine a duration of time that the power transistor is in the overload condition; and
assert a diagnostic signal in response to the duration of time being outside of a time window;
wherein the sense circuit comprises:
a first comparator configured to compare a voltage across the first and second conduction terminal of the transistor to a reference voltage and assert its output to indicate that the power transistor has entered the overload condition if the voltage across the first and second conduction terminals exceeds the reference voltage;
a counter configured to start in response to assertion of the output of the first comparator, and to stop at a final count in response to deassertion of the output of the first comparator; and
a comparison circuit configured to compare the final count to a threshold count indicative of the time window and assert the diagnostic signal based thereupon; and
wherein the comparison circuit comprises:
a first digital comparator configured to receive as input the upper threshold count and the final count, and to assert its output if the final count is greater than the upper threshold count;
a second digital comparator configured to receive as input the lower threshold count and the final count, and to assert its output if the final count is less than the lower threshold count; and
a logic circuit configured to assert the diagnostic signal in response to assertion of either the output of the first digital comparator or the output of the second digital comparator.