US 12,140,632 B2
Device under test synchronization with automated test equipment check cycle
Yongkang Hu, Xi'an (CN); Ramalingam Kolisetti, Karempudi (IN); Anubhav Sinha, Hyderabad (IN); and Abhijeet Samudra, Santa Clara, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Nov. 17, 2021, as Appl. No. 17/455,237.
Claims priority of provisional application 63/114,798, filed on Nov. 17, 2020.
Prior Publication US 2022/0155370 A1, May 19, 2022
Int. Cl. G01R 31/319 (2006.01); G01R 31/317 (2006.01); G01R 31/3183 (2006.01)
CPC G01R 31/31908 (2013.01) [G01R 31/31726 (2013.01); G01R 31/318307 (2013.01); G01R 31/31922 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
transmitting a test packet and a clock signal from an automated test equipment (ATE) to a first device under test (DUT), wherein the first DUT processes the test packet based on the clock signal;
receiving, at the ATE from the first DUT, a result packet; and
in response to receiving a start of packet (SOP) indicator from the first DUT at the ATE, evaluating the first DUT by comparing the result packet to an expected packet associated with the test packet, wherein the SOP indicator is based on a response clock for the first DUT.