US 12,140,624 B2
Semiconductor device and test system
Keita Takeuchi, Kanagawa (JP); Satoshi Yamamoto, Kanagawa (JP); Kyoichi Takenaka, Kanagawa (JP); and Keita Sasaki, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/904,723
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Jan. 5, 2021, PCT No. PCT/JP2021/000060
§ 371(c)(1), (2) Date Aug. 22, 2022,
PCT Pub. No. WO2021/171785, PCT Pub. Date Sep. 2, 2021.
Claims priority of application No. 2020-034246 (JP), filed on Feb. 28, 2020.
Prior Publication US 2023/0082419 A1, Mar. 16, 2023
Int. Cl. G01R 31/26 (2020.01)
CPC G01R 31/2607 (2013.01) 11 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a connection line that is-wired across a plurality of semiconductor substrates to be joined, wherein the plurality of semiconductor substrates corresponds to a plurality of detection target locations;
a plurality of detection circuits configured to output detection signals indicating detection results of the plurality of detection target locations, wherein each of the plurality of detection circuits is configured to:
detect presence or absence of an abnormality in a respective detection target location of the plurality of detection target locations; and
generate a respective detection signal of the detection signals based on an energization state of the connection line;
a result aggregation unit configured to:
aggregate the respective detection signal of each of the plurality of detection circuits; and
generate an output signal based on the aggregation of the respective detection signal of each of the plurality of detection circuits, wherein the output signal indicates the presence or the absence of the abnormality in at least one of the plurality of detection target locations.