US 12,140,022 B1
Downhole safety switch and communication protocol
Roger Jackson, Glendale, AZ (US); Brian Keith Roper, Phoenix, AZ (US); and Todd K. Roper, Glendale, AZ (US)
Assigned to Acuity Technical Designs, LLC, Phoenix, AZ (US)
Filed by Acuity Technical Designs, LLC, Phoenix, AZ (US)
Filed on Mar. 8, 2022, as Appl. No. 17/689,618.
Application 17/689,618 is a continuation in part of application No. 16/367,101, filed on Mar. 27, 2019, granted, now 11,268,376.
This patent is subject to a terminal disclaimer.
Int. Cl. E21B 47/12 (2012.01); E21B 43/1185 (2006.01); H04L 27/10 (2006.01)
CPC E21B 47/12 (2013.01) [E21B 43/1185 (2013.01); H04L 27/10 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A system comprising:
a surface device;
a downhole device; and
a wireline communication system including an addressable switch coupled to the downhole device, wherein the addressable switch comprises a first unique ID and a second unique ID;
wherein downlink communication between the surface device and the downhole device occurs via Hopped Frequency Shift Keying (HFSK) voltage-modulated signals, and wherein the addressable switch is configured to generate orientation data and communicate the first unique ID to the surface device in response to a signal from the surface device and is configured to transmit the second unique ID in response to the signal from the surface device; and
wherein the addressable switch is configured as a safety circuitry to arm a first detonator of the downhole device and a second detonator of a second downhole device, wherein the first unique ID is associated with the first detonator and the second unique ID is associated with the second detonator,
wherein a transport layer comprises a bit-stream with a Preamble, Sync, and Data Packet patterns, wherein the Data Packet pattern consists of Type, Address, Sequence, Command, Data, and Hash fields, wherein the Command comprises one of following: request device ID and version; Poll device for status, Downstream Switch Enable (DSSE); ARM Detonator; and FIRE, wherein the HFSK alternates between four different frequencies, F1, F2, F3, and F4, with a change in frequency indicating a new bit, and wherein the frequencies F1 and F2 are utilized for a Zero bit, and wherein the frequencies F3 and F4 are utilized for a One bit, excepting during the Preamble and the Sync patterns.