US 12,139,399 B2
Conductive bond structure to increase membrane sensitivity in MEMS device
Hung-Hua Lin, Taipei (TW); Chia-Ming Hung, Taipei (TW); Xin-Hua Huang, Xihu Township (TW); and Yuan-Chih Hsieh, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Mar. 29, 2022, as Appl. No. 17/706,863.
Application 17/706,863 is a division of application No. 16/601,749, filed on Oct. 15, 2019, granted, now 11,292,715.
Claims priority of provisional application 62/867,446, filed on Jun. 27, 2019.
Prior Publication US 2022/0219973 A1, Jul. 14, 2022
Int. Cl. B81C 3/00 (2006.01); B81B 3/00 (2006.01); B81B 7/00 (2006.01); B81B 7/02 (2006.01); B81C 1/00 (2006.01)
CPC B81C 3/001 (2013.01) [B81B 7/0006 (2013.01); B81B 2203/0127 (2013.01); B81B 2207/07 (2013.01); B81C 2201/0176 (2013.01); B81C 2203/019 (2013.01); B81C 2203/037 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming an integrated chip, the method comprising:
forming an interconnect structure over a first substrate;
forming a dielectric structure over the interconnect structure, wherein the dielectric structure comprises opposing sidewalls defining an opening;
forming a plurality of stopper structures over the interconnect structure and within the opening, wherein the stopper structures are formed concurrently with the dielectric structure;
forming a conductive bonding structure on a second substrate; and
performing a bonding process to bond the conductive bonding structure to the interconnect structure, wherein the conductive bonding structure is disposed in the opening, wherein the bonding process defines a first cavity between inner opposing sidewalls of the conductive bonding structure and a second cavity between the conductive bonding structure and the opposing sidewalls of the dielectric structure.