US 12,138,738 B2
Polishing pad, preparation method thereof and method for preparing semiconductor device using same
Jae In Ahn, Gyeonggi-do (KR); Kyung Hwan Kim, Gyeonggi-do (KR); Sung Hoon Yun, Gyeonggi-do (KR); Jang Won Seo, Gyeonggi-do (KR); and Kang Sik Myung, Gyeonggi-do (KR)
Assigned to SK ENPULSE CO., LTD., Gyeonggi-do (KR)
Filed by SK enpulse Co., Ltd., Gyeonggi-do (KR)
Filed on Jun. 16, 2021, as Appl. No. 17/349,285.
Claims priority of application No. 10-2020-0075101 (KR), filed on Jun. 19, 2020; and application No. 10-2020-0075102 (KR), filed on Jun. 19, 2020.
Prior Publication US 2021/0394334 A1, Dec. 23, 2021
Int. Cl. B24B 37/24 (2012.01); B24B 37/20 (2012.01); B24D 11/00 (2006.01); B24D 18/00 (2006.01); H01L 21/3105 (2006.01)
CPC B24B 37/24 (2013.01) [B24B 37/20 (2013.01); B24D 11/00 (2013.01); B24D 18/0009 (2013.01); H01L 21/31053 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A polishing pad, which satisfies Relationships 1 and 2 in an areal material ratio curve based on ISO 25178-2 standard after 25 dummy wafers are polished for 60 seconds each and two monitoring wafers are polished for 60 seconds each, each of the dummy and monitoring wafers being a silicon oxide wafer, while a calcined ceria slurry is sprayed at a rate of 200 cc/min on to the polishing pad during the polishing of the 25 dummy wafers and the two monitoring wafers, and wherein the polishing pad after the polishing is measured with an optical surface roughness meter:
0.020≤Vmp(10)/Vvv(80)≤1.000  [Relationship 1]
0.005≤Vmp(10)/Vmc(10,80)≤2.000  [Relationship 2]
in Relationships 1 and 2,
Vmp(10) is a material volume of peaks corresponding to an upper 10%,
Vvv(80) is a void volume of valleys corresponding to an upper 80% to 100%, and
Vmc(10,80) is a material volume of a core corresponding to an upper 10% to 80%.