| CPC G09G 3/20 (2013.01) [H03K 17/6871 (2013.01); G09G 2300/0443 (2013.01); G09G 2300/08 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/08 (2013.01)] | 23 Claims |
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[ 23. A display device, comprising:
a display panel that includes:
a plurality of gate lines;
a plurality of data lines; and
a plurality of subpixels; and
a plurality of gate circuits connected to the plurality of gate lines, wherein each of the plurality of gate circuits includes:
a first transistor connected to a Q node, the first transistor being between a first gate clock signal and a scan signal;
a second transistor connected to a QB node, the second transistor being between the scan signal and a first gate driving voltage;
a third transistor connected to a Q1 node, the third transistor being between a second gate clock signal and the QB node;
a fourth transistor connected to the second gate clock signal, the fourth transistor being between a third gate signal and the Q1 node; and
a first capacitor connected to the Q node.]
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