US 12,471,509 B2
Method of manufacturing a semiconductor device having three-dimensional cell structure
Jae Hyun Han, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on May 18, 2023, as Appl. No. 18/320,144.
Application 18/320,144 is a division of application No. 17/220,271, filed on Apr. 1, 2021, granted, now 11,696,520.
Claims priority of application No. 10-2020-0142565 (KR), filed on Oct. 29, 2020.
Prior Publication US 2023/0292638 A1, Sep. 14, 2023
Int. Cl. H10N 70/00 (2023.01); G11C 13/00 (2006.01)
CPC H10N 70/8828 (2023.02) [G11C 13/0004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); H10N 70/021 (2023.02); H10N 70/061 (2023.02); H10N 70/882 (2023.02); H10N 70/8825 (2023.02); H10N 70/8845 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate having a base insulation layer;
forming, over the base insulation layer, a plurality of first word line structures extending in a first lateral direction parallel to a surface of the substrate and a first switching functional layer disposed between the plurality of first word line structures, the plurality of first word line structures being spaced apart from each other in a second lateral direction, which is parallel to the surface of the substrate and perpendicular to the first lateral direction;
forming a first interlayer insulation layer on the plurality of first word line structures and the first switching functional layer;
forming, on the first interlayer insulation layer, a plurality of second word line structures extending in the first lateral direction and a second switching functional layer disposed between the plurality of second word line structures, the plurality of second word line structures arranged to overlap with the plurality of first word line structures, respectively;
performing selective etching to the second switching functional layer, the first interlayer insulation layer, the first switching functional layer, and the base insulation layer to form bit line contact holes exposing the substrate and to leave some portions of the first and second switching functional layers that remain on side surfaces of the plurality of first and second word line structures; and
providing a conductive material in the bit line contact holes to form bit line structures.