US 12,471,507 B2
Memory device and fabrication method thereof
Yu-Chao Lin, Hsinchu (TW); Tung-Ying Lee, Hsinchu (TW); and Shao-Ming Yu, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 3, 2022, as Appl. No. 17/857,023.
Prior Publication US 2024/0008375 A1, Jan. 4, 2024
Int. Cl. H10N 70/20 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/231 (2023.02) [H10B 63/84 (2023.02); H10N 70/021 (2023.02); H10N 70/063 (2023.02); H10N 70/841 (2023.02); H10N 70/8828 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate;
a seed layer over the substrate, wherein the seed layer comprises 95 wt % to 97 wt % carbon and 3 wt % to 5 wt % silicon;
a superlattice structure in contact with the seed layer, wherein the superlattice structure comprises a plurality of first metal layers and a plurality of second metal layers stacked alternately, wherein the plurality of first metal layers comprise Sb2Te3, and the plurality of second metal layers comprise an alloy comprising Ge and Te, and a bottom one of the plurality of first metal layers is in contact with the seed layer; and
a top electrode over the superlattice structure.