US 12,471,468 B2
Display substrate and display device
Weiyun Huang, Beijing (CN); Yao Huang, Beijing (CN); Chi Yu, Beijing (CN); Xingliang Xiao, Beijing (CN); Bo Shi, Beijing (CN); and Benlian Wang, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Chengdu (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Nov. 20, 2024, as Appl. No. 18/953,317.
Application 18/953,317 is a continuation of application No. 18/390,381, filed on Dec. 20, 2023, granted, now 12,232,380.
Application 18/390,381 is a continuation of application No. 17/297,641, granted, now 11,968,865, issued on Apr. 23, 2024, previously published as PCT/CN2020/080182, filed on Mar. 19, 2020.
Claims priority of application No. PCT/CN2020/073993 (WO), filed on Jan. 23, 2020; application No. PCT/CN2020/073995 (WO), filed on Jan. 23, 2020; application No. PCT/CN2020/073996 (WO), filed on Jan. 23, 2020; and application No. PCT/CN2020/074001 (WO), filed on Jan. 23, 2020.
Prior Publication US 2025/0089500 A1, Mar. 13, 2025
Int. Cl. H10K 59/131 (2023.01); G09G 3/3233 (2016.01); H10K 59/126 (2023.01); H10K 59/35 (2023.01); H10K 59/88 (2023.01)
CPC H10K 59/131 (2023.02) [G09G 3/3233 (2013.01); H10K 59/126 (2023.02); H10K 59/353 (2023.02); G09G 2300/0413 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0452 (2013.01); G09G 2300/0842 (2013.01); H10K 59/88 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A display substrate, comprising:
a base substrate, comprising a display region and a peripheral region which at least partially surrounds the display region, wherein the display region comprises a first display region, a second display region, and a third display region, the second display region surrounds the first display region, and the third display region at least partially surrounds the second display region;
a plurality of first pixel units, comprising a plurality of first light emitting elements in the first display region and a plurality of first pixel circuits in the second display region, wherein a first pixel circuit among the plurality of first pixel circuits is electrically connected to a corresponding first light emitting element among the plurality of first light emitting elements through a connecting wire, the first pixel circuit is configured to drive the corresponding first light emitting element, and orthographic projections of the plurality of first pixel circuits on the base substrate do not overlap with orthographic projections of the plurality of first light emitting elements on the base substrate;
a plurality of third pixel units in the third display region, wherein each third pixel unit comprises a third light emitting element and a third pixel circuit, the third pixel circuit is configured to drive a corresponding third light emitting element, and an orthographic projection of the third pixel circuit on the base substrate overlaps with an orthographic projection of the corresponding third light emitting element on the base substrate; and
at least one first signal line, which is at least located in the second display region and the third display region, wherein the first signal line comprises a first main body portion and a first winding portion, the first main body portion comprises a first sub-portion and a second sub-portion located on opposite sides of the first display region, respectively, the first winding portion is in the second display region and is electrically connected to the first sub-portion and the second sub-portion, respectively, the first winding portion comprises a fifth line portion, a sixth line portion, and a seventh line portion which are sequentially connected, the sixth line portion extends along a first direction, the fifth line portion and the seventh line portion extend along a second direction, and the first direction intersects with the second direction,
wherein the sixth line portion is electrically connected to the plurality of first pixel circuits; and
the sixth line portion at least partially overlaps with the plurality of first pixel circuits, or, the sixth line portion and the plurality of first pixel circuits are positioned in a same column and adjacent to each other but do not overlap with each other.