| CPC H10K 59/131 (2023.02) [G09G 3/3233 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0297 (2013.01)] | 20 Claims |

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1. A display substrate, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate; wherein the sub-pixels include:
a reset signal line, at least a part of the reset signal line extending along a first direction;
an initialization signal line, at least a part of the initialization signal line extending along the first direction;
a first transistor, a gate electrode of the first transistor being coupled to the reset signal line, a first electrode of the first transistor being coupled to the initialization signal line, an orthographic projection of at least part of the first electrode of the first transistor on the base substrate being located between an orthographic projection of the reset signal line on the base substrate and an orthographic projection of the initialization signal line on the base substrate.
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