US 12,471,414 B2
LED chip and preparation method therefor
Sibo Wang, Jiangsu (CN); Dongmei Li, Jiangsu (CN); and Han-Chung Liao, Jiangsu (CN)
Assigned to HUAIAN AUCKSUN OPTOELECTRONICS TECHNOLOGY CO., LTD, Jiangsu (CN)
Appl. No. 18/256,173
Filed by HUAIAN AUCKSUN OPTOELECTRONICS TECHNOLOGY CO., LTD, Jiangsu (CN)
PCT Filed Dec. 15, 2021, PCT No. PCT/CN2021/138501
§ 371(c)(1), (2) Date Jun. 6, 2023,
PCT Pub. No. WO2023/060753, PCT Pub. Date Apr. 20, 2023.
Claims priority of application No. 202111198536.5 (CN), filed on Oct. 14, 2021; and application No. 202122479725.1 (CN), filed on Oct. 14, 2021.
Prior Publication US 2024/0038936 A1, Feb. 1, 2024
Int. Cl. H10H 20/831 (2025.01); H01L 25/075 (2006.01); H10H 20/01 (2025.01); H10H 20/816 (2025.01); H10H 20/841 (2025.01); H10H 20/857 (2025.01)
CPC H10H 20/8312 (2025.01) [H01L 25/0753 (2013.01); H10H 20/8162 (2025.01); H10H 20/841 (2025.01); H10H 20/857 (2025.01); H10H 20/032 (2025.01); H10H 20/034 (2025.01); H10H 20/0364 (2025.01)] 15 Claims
OG exemplary drawing
 
1. An LED chip, wherein the LED chip comprises:
a substrate;
an epitaxial wafer with a PN step, wherein the epitaxial wafer comprises an N-type semiconductive layer, a light-emitting layer and a P-type semiconductive layer;
at least one first P-type electrode, located on the PN step and in electrical connection with the P-type semiconductive layer;
at least one first N-type electrode, located on the N-type semiconductive layer and in electrical connection with the N-type semiconductor layer;
a first insulation layer, covering the first N-type electrode, the PN step, the first P-type electrode and the N-type semiconductive layer, and provided with a plurality of first through holes and a plurality of second through holes;
second P-type electrodes, disposed on the first insulation layer and in electrical connection with the first P-type electrode through the first through holes;
second N-type electrodes, disposed on the first insulation layer and in electrical connection with the first N-type electrode through the second through holes;
a second insulation layer, covering the second P-type electrodes, the second N-type electrodes and the first insulation layer, and provided with a plurality of third through holes and a plurality of fourth through holes;
third P-type electrodes, disposed on the second insulation layer and in electrical connection with the second P-type electrodes through the third through holes;
third N-type electrodes, disposed on the second insulation layer, and in electrical connection with the second N-type electrodes through the fourth through holes;
P-type pads, disposed on the third P-type electrodes and in electrical connection with the third P-type electrodes; and
N-type pads, disposed on the third N-type electrodes and in electrical connection with the third N-type electrodes.