US 12,471,411 B2
Method for manufacturing optoelectronic devices
Francois Roy, Seyssins (FR)
Assigned to STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed by STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed on Apr. 27, 2023, as Appl. No. 18/140,100.
Claims priority of application No. 2204145 (FR), filed on May 2, 2022.
Prior Publication US 2023/0361241 A1, Nov. 9, 2023
Int. Cl. H10H 20/01 (2025.01); H01L 21/02 (2006.01); H10F 71/00 (2025.01)
CPC H10H 20/018 (2025.01) [H01L 21/02455 (2013.01); H01L 21/02469 (2013.01); H10F 71/1257 (2025.01); H10F 71/1276 (2025.01); H10F 71/137 (2025.01); H10H 20/012 (2025.01); H10H 20/0125 (2025.01); H10H 20/013 (2025.01); H10H 20/0133 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A manufacturing method, comprising:
providing a plurality of first layers covering a first support;
wherein each first layer is made of a first semiconductor material;
wherein the first layers are spaced apart from each other;
epitaxially growing, on each first layer, a second layer made of a second semiconductor material;
epitaxially growing, on each second layer, a stack of semiconductor layers;
wherein said stack of semiconductor layers comprises a third layer made of a third semiconductor material in physical contact with the second layer;
etching the second layer to separate each stack of semiconductor layers from the first layer;
wherein said etching is selective simultaneously over both the first and third semiconductor materials; and
transferring each separated stack of semiconductor layers onto a second support;
wherein each of the first and third semiconductor materials is one of a III-V compound or a II-VI compound.