US 12,471,409 B2
Monolithic electronic device
John Whiteman, Plymouth (GB)
Assigned to Plessey Semiconductors Limited, Plymouth (GB)
Appl. No. 17/801,100
Filed by PLESSEY SEMICONDUCTORS LIMITED, Plymouth (GB)
PCT Filed Mar. 25, 2021, PCT No. PCT/EP2021/057713
§ 371(c)(1), (2) Date Aug. 19, 2022,
PCT Pub. No. WO2021/198009, PCT Pub. Date Oct. 7, 2021.
Claims priority of application No. 2004610 (GB), filed on Mar. 30, 2020.
Prior Publication US 2023/0075038 A1, Mar. 9, 2023
Int. Cl. H01L 21/66 (2006.01); G01R 1/04 (2006.01); H10H 20/01 (2025.01); H10H 20/82 (2025.01); H10H 20/825 (2025.01); H10H 20/851 (2025.01); H10H 29/14 (2025.01)
CPC H10H 20/01 (2025.01) [G01R 1/0408 (2013.01); H10H 20/018 (2025.01); H10H 20/82 (2025.01); H10H 20/825 (2025.01); H10H 20/851 (2025.01); H10H 29/142 (2025.01); H10H 20/0361 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming and testing a plurality of monolithic electronic devices, the method comprising:
a) forming a monolithic electronic device array comprising:
forming a common semiconducting layer comprising a Group III-nitride on a sacrificial substrate;
forming an array of monolithic electronic devices on a surface of the common semiconducting layer on an opposite side of the common semiconducting layer to the sacrificial substrate, each monolithic electronic device of the array of monolithic electronic devices comprising a plurality of Group III-nitride layers;
forming a planarising dielectric layer over the array of monolithic electronic devices to provide a planarised dielectric surface which is generally aligned with the surface of the common semiconducting layer;
forming a grid of trenches by etching the planarising dielectric layer and the common semiconducting layer from the planarised dielectric surface through to the sacrificial substrate, wherein the grid of trenches surrounds each monolithic electronic device;
forming first electrical contacts to each monolithic electronic device through the planarising dielectric layer,
forming a sacrificial dielectric layer over the grid of trenches and the planarised dielectric surface of the planarising dielectric layer to form a first bonding surface generally aligned with the surface of the common semiconducting layer, wherein the first bonding surface comprises first apertures aligned with each of the first electrical contacts;
b) providing a test substrate comprising:
an electronics substrate comprising electronics testing circuitry configured to supply power to each of the monolithic electronic devices of the monolithic electronic device array;
and
a plurality of second electrical contacts arranged on the electronics substrate to correspond to an arrangement of the first electrical contacts of the monolithic electronic device array;
wherein a bonding dielectric layer is formed on the electronics substrate to provide a second bonding surface, the second bonding surface comprising second apertures aligned with each of the second electrical contacts;
c) aligning the second electrical contacts of the test substrate with the first electrical contacts of the monolithic electronic device array and bonding the second bonding surface of the test substrate to the first bonding surface of the sacrificial dielectric layer such that the first and second electrical contacts are in electrical contact;
d) supplying power from the test substrate to the monolithic electronic device array to test each of the monolithic electronic devices of the monolithic electronic device array via the plurality of first and second electrical contacts; and
e) selectively removing first portions of the sacrificial substrate through a thickness of the sacrificial substrate to separate each of the monolithic electronic devices; and
removing the sacrificial dielectric layer to separate each monolithic electronic device from the test substrate.