US 12,471,401 B2
Image sensor package
Kyongsoon Cho, Incheon (KR); and Ikjun Choi, Cheonan-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 8, 2022, as Appl. No. 18/063,268.
Claims priority of application No. 10-2022-0022457 (KR), filed on Feb. 21, 2022.
Prior Publication US 2023/0268370 A1, Aug. 24, 2023
Int. Cl. H10F 39/00 (2025.01)
CPC H10F 39/811 (2025.01) [H10F 39/809 (2025.01); H01L 2224/0812 (2013.01); H01L 2224/08123 (2013.01); H01L 2224/08135 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/08147 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An image sensor package comprising:
a first substrate portion comprising a first substrate and an upper wiring structure, the first substrate including a first surface and a second surface opposite to the first surface, the first substrate comprising a sensor portion, a plurality of active pixels in the sensor portion, the upper wiring structure on the first surface of the first substrate, and the upper wiring structure comprising a stacked structure including a plurality of upper wiring patterns and a plurality of upper wiring vias;
a second substrate portion comprising a second substrate and a lower wiring structure, the second substrate including a third surface and a fourth surface opposite to the third surface, the second substrate defining a trench portion extending inward from the fourth surface of the second substrate, the second substrate defining a via hole extending from a bottom surface of the trench portion to the third surface of the second substrate, the lower wiring structure on the third surface of the second substrate, and the lower wiring structure comprising a stacked structure including a plurality of lower wiring patterns and a plurality of lower wiring vias, wherein the lower wiring structure is in contact with the upper wiring structure, the plurality of lower wiring patterns comprise a plurality of lower patterns at different vertical levels; and
a via electrode portion covering an inner sidewall and a bottom surface of the via hole, the via electrode portion extending into the lower wiring structure and connected to at least a portion of the plurality of lower wiring patterns, and, in the lower wiring structure, the via electrode portion entirely overlaps at least two of the plurality of lower patterns in a vertical direction, the at least two of the plurality of lower patterns at different vertical levels.