US 12,471,384 B2
Protection device with space saving layout
Rolf Weis, Dresden (DE); Josef Deichler, Dresden (DE); Henning Feick, Dresden (DE); and Ahmed Mahmoud, Freising (DE)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Nov. 15, 2022, as Appl. No. 17/987,225.
Application 17/987,225 is a continuation in part of application No. 17/882,915, filed on Aug. 8, 2022.
Claims priority of application No. 21191573 (EP), filed on Aug. 16, 2021; and application No. 22188085 (EP), filed on Aug. 1, 2022.
Prior Publication US 2023/0071856 A1, Mar. 9, 2023
Int. Cl. H10D 89/60 (2025.01); H10D 8/00 (2025.01); H10D 8/01 (2025.01); H10D 62/10 (2025.01); H10D 62/83 (2025.01)
CPC H10D 89/611 (2025.01) 9 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first diode arrangement including at least one first diode and at least one second diode connected in anti-series between a first circuit node and a second circuit node of the first diode arrangement;
forming a second diode arrangement including at least one first diode and at least one second diode connected in anti-series between a first circuit node and a second circuit node of the second diode arrangement; and
connecting the second circuit node of the first diode arrangement and the second circuit node of the second diode arrangement,
wherein forming the first diode arrangement comprises implanting first type dopant atoms into a first polysilicon layer in a first implantation process using a first implantation mask to form first implanted regions, and implanting second type dopant atoms into the first polysilicon layer in a second implantation process and using a second implantation mask to form at least one second implanted region, wherein the first implanted regions and the at least one second implanted region are arranged alternatingly in a first direction and are separated from one another by third regions of the first polysilicon layer,
wherein forming the second diode arrangement comprises implanting first type dopant atoms into a second polysilicon layer in the first implantation process using the first implantation mask to form first implanted regions, and implanting second type dopant atoms into the second polysilicon layer in the second implantation process and using the second implantation mask to form at least one second implanted region, wherein the first implanted regions and the at least one second implanted region are arranged alternatingly in the first direction and are separated by third regions of the second polysilicon layer, and
wherein in each of the first and second diode arrangements, the respective second circuit node is spaced apart from the respective first circuit node in the first direction,
wherein in a plan-view of the first and second diode arrangements, the first polysilicon layer and the second polysilicon layer are each enclosed regions that are spaced apart from one another.