US 12,471,382 B2
ESD protection circuit
Aurelie Arnaud, Saint-Cyr-sur-Loire (FR); and Andrea Brischetto, Catania (IT)
Assigned to STMicroelectronics (Tours) SAS, Tours (FR); and STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics (Tours) SAS, Tours (FR); and STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Nov. 2, 2022, as Appl. No. 18/052,158.
Application 18/052,158 is a division of application No. 16/353,658, filed on Mar. 14, 2019, granted, now 11,515,301.
Claims priority of application No. 1852428 (FR), filed on Mar. 21, 2018.
Prior Publication US 2023/0290770 A1, Sep. 14, 2023
Int. Cl. H10D 89/00 (2025.01); H10D 8/00 (2025.01); H10D 62/83 (2025.01); H10D 89/60 (2025.01)
CPC H10D 89/60 (2025.01) [H10D 8/00 (2025.01); H10D 62/83 (2025.01); H10D 89/611 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first cavity and a second cavity in an upper surface of a semiconductor substrate;
forming a first epitaxial silicon region in the first cavity and a second epitaxial silicon region in a second cavity, each of the first and second epitaxial regions having an upper surface;
forming a first doped silicon region in the upper surface of the first epitaxial silicon region and a second doped silicon region in the upper surface of the second epitaxial silicon region, each of the first and second doped silicon regions having an upper surface;
forming an epitaxial layer on the upper surface of the semiconductor substrate, on the upper surfaces of the first and second epitaxial silicon regions, and on the upper surfaces of the first and second doped silicon regions, the epitaxial layer having an upper surface;
forming a third doped silicon region and a fourth doped silicon region in the upper surface of the epitaxial layer, the third doped silicon region being over the first epitaxial silicon region and the fourth doped silicon region being over the second epitaxial silicon region; and
forming, in the upper surface of a portion of the epitaxial layer over a portion of the semiconductor substrate between the first and second cavities, a fifth doped silicon region and a sixth doped silicon region.