| CPC H10D 89/10 (2025.01) [G06F 30/392 (2020.01)] | 11 Claims |
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1. A semiconductor device comprising:
a logical cell;
a spare cell configuring a new logical function in combination with the logical cell in event of design change; and
a potential fix cell outputting a reference potential used for fixing a potential of an input wiring of the spare cell,
wherein the potential fix cell includes:
a mutual connection wiring;
a first wiring formed in an upper layer of the mutual connection wiring and connected with the mutual connection wiring;
a second wiring formed in an upper layer of the mutual connection wiring and connected with the mutual connection wiring; and
an output wiring formed in an upper layer of the first wiring and connected with the first wiring,
wherein the second wiring has a power supply potential, and is wired at a cell boundary between the potential fix cell and an adjacent different cell, in a lower layer of the output wiring,
wherein the first wiring is wired to be closer to inside of the potential fix cell than the second wiring, and
wherein the output wiring outputs the reference potential in response to reception of the power supply potential through the second wiring, the mutual connection wiring and the first wiring.
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