US 12,471,379 B2
Multi-function substrate
Eugene I-Chun Chen, Taipei (TW); Kuan-Liang Liu, Pingtung (TW); Szu-Yu Wang, Hsinchu (TW); Chia-Shiung Tsai, Hsin-Chu (TW); Ru-Liang Lee, Hsinchu (TW); Chih-Ping Chao, Hsin-Chu (TW); and Alexander Kalnitsky, San Francisco, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 13, 2024, as Appl. No. 18/741,863.
Application 17/869,827 is a division of application No. 17/189,709, filed on Mar. 2, 2021, granted, now 11,532,642, issued on Dec. 20, 2022.
Application 18/741,863 is a continuation of application No. 17/869,827, filed on Jul. 21, 2022, granted, now 12,113,071.
Claims priority of provisional application 63/124,983, filed on Dec. 14, 2020.
Prior Publication US 2024/0332306 A1, Oct. 3, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 87/00 (2025.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01)
CPC H10D 87/00 (2025.01) [H01L 21/76275 (2013.01); H01L 21/76283 (2013.01); H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/02658 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
an epitaxial layer arranged on a semiconductor body;
a trap-rich layer arranged on the epitaxial layer;
a dielectric layer arranged on the trap-rich layer;
an active semiconductor layer arranged on the dielectric layer; and
a semiconductor material arranged on the epitaxial layer and laterally beside the active semiconductor layer, wherein the epitaxial layer continuously extends from directly below the trap-rich layer to directly below the semiconductor material.