US 12,471,377 B2
Method of forming semiconductor device having segmented interconnect
Chih-Yu Lai, Hsinchu (TW); Chih-Liang Chen, Hsinchu (TW); Ching-Wei Tsai, Hsinchu (TW); Shang-Wen Chang, Hsinchu (TW); and Li-Chun Tien, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 26, 2024, as Appl. No. 18/755,041.
Application 18/755,041 is a division of application No. 17/463,022, filed on Aug. 31, 2021, granted, now 12,034,009.
Prior Publication US 2024/0347546 A1, Oct. 17, 2024
Int. Cl. H10D 86/60 (2025.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H10D 30/67 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 88/00 (2025.01)
CPC H10D 86/60 (2025.01) [H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H10D 86/021 (2025.01); H10D 86/441 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of making a semiconductor device, the method comprising:
depositing a base isolation layer;
manufacturing a first bridge pillar extending through the base isolation layer;
manufacturing a first transistor on a first side of the base isolation layer, including:
manufacturing a first transistor channel bar, and
manufacturing a first transistor source/drain electrode (S/D electrode), wherein the first transistor S/D electrode electrically connects to the first bridge pillar on the first side of the base isolation layer;
manufacturing a second transistor on a second side of the base isolation layer, including:
manufacturing a second transistor channel bar, and
manufacturing a second transistor S/D electrode;
manufacturing a first metal electrode on the second side of the base isolation layer, wherein:
the first bridge pillar electrically connects the first transistor S/D electrode on the first side of the base isolation layer to the first metal electrode on the second side of the base isolation layer;
manufacturing a first via electrically connected to the first metal electrode; and
manufacturing a first conductive line electrically connected to the first via,
wherein:
the first transistor S/D electrode and the second transistor S/D electrode are formed to be spaced apart by a first height in a first direction,
the first metal electrode is formed to be separated from the second transistor S/D electrode in a second direction perpendicular to the first direction,
the first bridge pillar is formed to be separated from the second transistor S/D electrode in the second direction, and
the first bridge pillar is formed to have a height in the first direction substantially equal to the first height.