US 12,471,373 B2
Array substrate and display panel
Lizhong Wang, Beijing (CN); Ce Ning, Beijing (CN); Tianmin Zhou, Beijing (CN); Wei Yang, Beijing (CN); Yunping Di, Beijing (CN); Rui Huang, Beijing (CN); Binbin Tong, Beijing (CN); and Liping Lei, Beijing (CN)
Assigned to BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., Beijing (CN)
Appl. No. 17/919,547
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Nov. 17, 2021, PCT No. PCT/CN2021/131314
§ 371(c)(1), (2) Date Oct. 18, 2022,
PCT Pub. No. WO2022/193702, PCT Pub. Date Sep. 22, 2022.
Claims priority of application No. 202120565402.1 (CN), filed on Mar. 19, 2021.
Prior Publication US 2023/0163143 A1, May 25, 2023
Int. Cl. H10D 86/60 (2025.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); H10D 86/40 (2025.01)
CPC H10D 86/60 (2025.01) [G02F 1/136209 (2013.01); G02F 1/136295 (2021.01); G02F 1/13685 (2021.01); H10D 86/423 (2025.01); H10D 86/441 (2025.01); H10D 86/471 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a base substrate; and
a thin film transistor group arranged on a side of the base substrate, wherein the thin film transistor group comprises at least two thin film transistors, and the thin film transistors are stacked in a direction perpendicular to the base substrate,
wherein the thin film transistor group comprises a first thin film transistor and a second thin film transistor, the first thin film transistor comprises a first active layer and a first source and drain layer, and the second thin film transistor comprises a second active layer and a second source and drain layer; and
wherein the first source and drain layer comprises a first pole and a second pole, the first active layer comprises a first subsection and a second subsection, the first subsection and the second subsection have a first included angle, the first subsection is connected to the first pole, and the second subsection is connected to the second pole.