US 12,471,372 B2
Back plate and anode back plate for 3D printing
Yitong Guo, Beijing (CN); Jian Zhou, Beijing (CN); Tuo Sun, Beijing (CN); and Xiaochun Xu, Beijing (CN)
Assigned to Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 17/770,590
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Mar. 15, 2021, PCT No. PCT/CN2021/080744
§ 371(c)(1), (2) Date Apr. 20, 2022,
PCT Pub. No. WO2022/062330, PCT Pub. Date Mar. 31, 2022.
Claims priority of application No. 202011023517.4 (CN), filed on Sep. 25, 2020; application No. 202011023605.4 (CN), filed on Sep. 25, 2020; and application No. 202011025488.5 (CN), filed on Sep. 25, 2020.
Prior Publication US 2023/0021559 A1, Jan. 26, 2023
Int. Cl. H10D 86/60 (2025.01); H10D 86/40 (2025.01)
CPC H10D 86/60 (2025.01) [H10D 86/441 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A back plate, comprising a base substrate, gate lines, data lines and power supply lines arranged on the base substrate crossing each other in rows and columns, and pixel structures arranged in an array on the base substrate, wherein
each pixel structure includes a driving transistor, a switching transistor connected to the driving transistor, and a pixel electrode connected to the driving transistor; a gate line and a data line are connected to the switching transistor, and a power supply line is connected to the driving transistor;
in a same row of pixel structures or a same column of pixel structures, a power supply line is arranged between an (2n−1)th pixel structure and an 2n-th pixel structure, and the power supply line is connected to a source electrode of a driving transistor in the (2n−1)th pixel structure and a source electrode of a driving transistor in the 2n-th pixel structure; n is a positive integer greater than or equal to 1;
wherein, in a pixel area where the pixel structure is located, the driving transistor and the switching transistor are arranged in sequence along the column direction,
a gate electrode of the driving transistor extends in the row direction from the data line to the power supply line, and the gate electrode of the driving transistor extends in the column direction from the gate line of a previous row of pixel structures to the switching transistor;
a width direction of a channel in an active layer pattern of the driving transistor is consistent with the row direction, and the channel extends in the row direction from the data line arranged on one side of the pixel structure to the power supply line arranged on the other side of the pixel structure;
the gate electrode of the driving transistor is connected to a drain electrode of the switching transistor, the source electrode of the driving transistor is electrically connected to the power supply line, and the drain electrode of the driving transistor is electrically connected to the pixel electrode;
a source electrode of the switching transistor is electrically connected to the data line, and a gate electrode of the switching transistor is electrically connected to a gate line;
wherein a length of the gate electrode of the driving transistor in the column direction is greater than a length of the active layer pattern of the driving transistor in the column direction, so that the gate electrode of the driving transistor extends towards the switching transistor relative to the active layer thereby forming an extension portion of the gate electrode of the driving transistor, and orthographic projections of the extension portion of the gate electrode and the active layer pattern of the driving transistor on the base substrate are non-overlapping with each other;
the drain electrode of the driving transistor is electrically connected to the pixel electrode through a capacitor electrode layer;
orthographic projections of the capacitor electrode layer and the extension portion on the base substrate at least partially overlap with each other, and the capacitor electrode layer at least forms a capacitance with the extension portion of the gate electrode.